MCA-3K Data Server (sipm-MDS) Reference

eMorpho

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USB driver

bpi_device

Data structures

Overview

Module Constants

FPGA Data structures

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Histogram

List Mode

Oscilloscope Trace

Summation Weights

Time Slices

Two-bank List Mode

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API

Overview

MCA-3K Data Structure: fpga_ctrl

Summary

The fpga_ctrl data structure contains the data used to control the parameters of FPGA-based data acquisition. Actions such as start/stop data acquisition are communicated via the fpga_action structure.

Data structure

For fpga_ctrl there are 16 'register' and a larger number of named 'field' data in use. All register data are 16-bit unsigned int16 (uint16).

fpga_ctrl registers and fields
Register number and field nameDescription
CR0[0:15]: fine_gainComponent of the digital gain. Range is 0 to 65535. A value of 32768 corresponds to unity gain.
CR1[0:9]: baseline_thresholdA trigger threshold for pulse height above baseline. Pulse heights below this value will be considered to be part of the DC baseline and are added to the DC-offset average. Unit is 0.978mV, 1023 →1.0V.
CR1[10:15]: cr1_upperUnused; set to zero
CR2[0:9]: pulse_thresholdA signal trigger threshold for pulse height above baseline. Pulse heights above this value will be considered to be a signal and the FPGA will attempt to measure the pulse energy. The meaning of an LSB is the same as for baseline_threshold, above.
CR2[10:15]: cr2_upperUnused; set to zero
CR3[0:15]: hold_off_timeEnforced minimum trigger dead time after a recognized pulse trigger. Unit: 1 ADC sampling clock cycle (ie 25ns for a 40MSPS system)
CR4[0:15]: integration_timePulse summation time to measure pulse energy. Unit: 1 ADC sampling clock cycle (ie 25ns for a 40MSPS system)
CR5[0:15]: roi_boundsRegion of interest bit-field: (A,B), B and A are 8-bit numbers. The region of interest is [16*A, 16*B] in mathematical notation.
CR6[0:9]: trigger_delayNumber of pre-trigger ADC samples stored with a recorded scintillator pulse, called a trace
CR6[10:15]: cr6_upperUnused; set to zero
CR7[0:15]: ctrl_7Unused; set to zero
CR8[0:15]: run_time_0See below
CR9[0:15]: run_time_1RT = run_time_0 + 65536*run_time_1
It is a requested runtime for histogram data acquisition. Unit is 65536/ADC_sampling_rate; eg 1.6384ms for a 40MHz device.
The exact meaning depends on rtlt-value: 0 → ignored; DAQ continues indefinitely, 1 → limit is DAQ live time, 2 → limit is DAQ real time, 3 → DAQ stops at request number of accepted events
CR10[0:15]: short_itA summation interval shorter than integration_time. It is used together with list mode (lm_mode=1) or other on-the-fly pulse shape discrimination. Unit: 1 ADC sampling clock cycle (ie 25ns for a 40MSPS system)
CR11[0:15]: putPileup parameter; Content depends on the value of nai_mode. 0 → pile up inspection is turned off.
CR12[0:3]: ecompCoarse-gain part of digital gain; each unit divides the energy by 2 before binning in the energy histogram.
Digital_Gain = fine_gain / 2ecomp * 40MHz/ADC_SR
CR12[4:7]: pcompCoarse-gain for PID-entries in list-mode;
CR12[8:11]: gain_selectSelect transimpedance (Z, gain) of input amplifier; 0 →100Ω, 1 →430Ω, 2 →1100Ω, 4 →3400Ω, 8 →10100Ω V_out = Z*I_SiPM; ADC has 1V input range.
CR12[12:15]: cr12_upperUnused; Set to zero
CR13[0:15]: ctrl_13Unused; Set to zero
CR13[2]: suspendHalt all operation, event and time counters;
CR14[0:15]: LED control Implemented for those units with an integrated LED.Below, SR is the ADC sampling rate, which most often is 40MHz.
CR14[0:4]: led_repeat_time LED pulse frequency = SR/(2(T+2))
CR14[5:8]: led_pulse_width LED pulse frequency = SR/(2(W+1))
CR14[9:12]: led_pulse_sep LED pulse frequency = SR/(2(S+1))
CR14[13]: cr14b13 Unused
CR14[14]: led_trigger 1→ Issue event trigger when LED fires. Set to 0.
CR14[14]: led_enable 1→ Turn LED ON.
CR15[0]: ha_modeSelect quantity to histogram: 0 → energy, 1 →amplitude, ie pulse height in mV.
CR15[1]: trace_modeOscilloscope trace acquisition mode: 0 → triggered, 1 → validated, ie not out of range, not pileup-rejected.
CR15[2]: lm_modeSelects event data format in listmode data acquisition. 0 → (16-bit energy, 32-bit time), 1 → (16-bit energy, 16-bit PID, 16-bit time).
CR15[3]: sel_ledUnused; Set to 0
CR15[4:5]: rtltcf request, above.
CR15[6]: suspend0 → Normal operation. 1 → Halt all timers and data acquisition.
CR15[7]: daq_mode0 → Statistics counters continue after DAQ run has stopped; 1 → They stop when DAQ stops;
CR15[8]: nai_modeSelect a method of pile up rejection; 0 → Good for all scintillators (especially slow ones); 1 → Optimized for fast scintillators (τ < 1µs). Affects the choice of PUT value.
The fpga_ctrl registers; CRn means control register number n, with n=0...15 . Bitfields are indicated as [b_low:b_high] indicating bit numbers b_low to b_high, inclusive.

The user dictionary is used to convert some fpga_ctrl registers in to physical quantities, mostly amplitudes(V) and times(s).

fpga_ctrl user dictionary
Register number and field nameDescription
digital_gainDigital_Gain = fine_gain / 2ecomp * 40MHz/ADC_SR
integration_timeSummation time to measure the pulse energy
hold_off_timeEnforced minimum dead time after a trigger. Used to avoid retriggering on the falling edge of a pulse.
short_itShort integration time. Used for pulse shape discrimination.
baseline_thresholdPulse heights smaller than this values will be considered to be DC-offset baseline noise signals.
pulse_thresholdMinimum signal height to trigger an energy measurement.
trigger_delayAmount of pre-trigger trace data shown in a recorded trace. Increasing trigger_delay pushes the displayed pulse to the right.
roi_low, roi_highThe region of interest is [16*roi_low, 16*roi_high] in mathematical notation.
run_timeEither run time in seconds, or maximum number of counts in the histogram; cf request and rtlt in the table above.
The fpga_ctrl registers; CRn means control register number n, with n=0...15 . Bitfields are indicated as [b_low:b_high] indicating bit numbers b_low to b_high, inclusive.